1. Field of Invention
The present invention relates to an active device array substrate, and particularly to an active device array substrate with an electrostatic discharge (ESD) protection circuit.
2. Description of the Related Art
Along with the modern video technology progress, liquid crystal display (LCD) apparatuses have been largely used as display screens in various electronic products, such as mobile phones, notebook computers, PCs and personal digital assistants (PDAs). In general, an LCD includes a thin film transistor (TFT) array substrate, a color filter substrate and a liquid crystal layer, wherein the TFT array substrate and the color filter substrate are assembled together, and the liquid crystal layer is located between the TFT array substrate and the color filter substrate. By means of all the TFTs in the TFT array substrate to modulate the orientations of the liquid crystal molecules in the liquid crystal layer, the light beam intensity is controlled for displaying images.
During a process for fabricating an LCD apparatus, however, the manufacturing equipment, the operators and the TFT array substrate itself are likely accumulated with a lot of electrostatic discharges, i.e. ESD stressed. Thus, once the TFT array substrate is contacted with the manufacturing equipment, the operators or other charged objects during the production process, an ESD phenomenon is triggered. Due to the fine conductive traces and elements of a TFT array substrate, a minor ESD event often causes a serious result where the affected LCD apparatus is entirely discarded. In order to solve the problem that an ESD event damages an LCD apparatus, a TFT array substrate usually includes an ESD protection circuit.
FIG. 1 is a diagram of a conventional TFT array substrate. Referring to FIG. 1, a conventional TFT array substrate 100 includes pixel units 110, scan lines 120, data lines 130, bonding pads 140, back-to-back diodes 150 and a short ring 160. Each pixel unit 110 includes a TFT 112 and a pixel electrode 114, and the pixel units 110 arranged in an array are electrically connected to the corresponding scan lines 120 and data lines 130, respectively. An end of each scan line 120 and an end of each data line 130 are electrically connected to the corresponding bonding pads 140, while the bonding pads 140 are electrically connected to the short ring 160 via the corresponding back-to-back diodes 150.
The back-to-back diode 150 has a turned on voltage which is adding up a forward-biased voltage of a diode and a reveries-biased voltage of a diode. When an ESD stress occurs on the TFT array substrate 100, the voltage of the built-up electrostatic charges is usually larger than the turn-on voltage of the back-to-back diode 150 so as to turn on the back-to-back diode 150. Consequently, the electrostatic charges would be conducted to the short ring 160 through the back-to-back diode 150, so as to avoid the electrostatic charges from flowing into the pixel units 110 to damage the TFTs 112. On the other hand, during testing the TFT array substrate 100, the testing operation voltage is normally not larger than the turn-on voltage of the back-to-back diode 150, thus an open circuit status is presented between the bonding pad 140 and the short ring 160. That is, there is no interactive voltage influence between the scan line 120 and the data line 130 to affect the normal operations of the pixel units 110.
In order to avoid large current leakage occurs in the back-to-back diode 150 to affect the operation signals between the scan line 120 and the data line 130, it is better that the turned on voltage of the back-to-back diode 150 is larger so as to reduce the effect to the TFT array substrate 100. However, if the turned on voltage of the back-to-back diode 150 is increased, the pixel units 110 are damaged by the ESD charges when the TFT array substrate 100 is subjected to the ESD stress occurred inside or outside the TFT array substrate 100. Therefore, how to design the turned on voltage of the back-to-back diode 150 is important.
After the TFT array substrate 100 is completely fabricated, the wiring circuits between all the bonding pads 140 and the short ring 160 are electrically cut off, following by the subsequent processes. During the successive assembly process however, the TFT array substrate 100 likely accumulates electrostatic charges, and at the point, the TFT array substrate 100 has disabled the ESD protection function already, which puts the TFT array substrate 100 in jeopardy to be damaged by an ESD event.
FIG. 2 is a diagram of another conventional TFT array substrate. Referring to FIG. 2, the conventional TFT array substrate 200 includes pixel units 210, scan lines 220, data lines 230, bonding pads 240, bi-forward diodes 250 and a first short ring 260, a second short ring 270 and a power control circuit 280. The pixel units 210 are electrically connected to the corresponding scan lines 220 and data lines 230, respectively. An end of each scan line 220 and an end of each data line 230 are electrically connected to the corresponding bonding pads 240. Each of the bi-forward diodes 250 includes two diodes 250a and 250b, while the bonding pads 240 are electrically connected to the first short ring 260 via the corresponding diodes 250a and then electrically connected to the second short ring 270 via the corresponding diodes 250b. In addition, the power control circuit 280 is electrically connected to the first short ring 260 and the second short ring 270.
As an ESD event occurs, all of the three voltage levels of the power supply 290 are 0V. When the accumulated electrostatic charges are conducted to the first short ring 260 via the diode 250a or 250b and then conducted to the second short ring 270 through the power control circuit 280, the ESD charges are rapidly transferred to the lowest voltage level on the TFT array substrate 200. Thereby, the accumulated electrostatic charges are neutralized so as to avoid the accumulated electrostatic charges from flowing into the pixel units 210 on the TFT array substrate 200 to cause fatal failure. On the other hand, prior to operating the TFT array substrate 200, a power supply 290 is electrically connected to the ESD protection circuit 280 to provide the ESD protection circuit 280 with a high voltage Vdd, a low voltage Vss and a medium voltage Vm. Hence, the ESD protection circuit 280 is able to keep the first short ring 260 in the high voltage Vdd and keep the second short ring 270 in the low voltage Vss. Note that the operation voltage for the TFT array substrate 200 is between the high voltage Vdd and the low voltage Vss, thus each diode 250a and each diode 250b are reversely biased, which establishes open circuit statuses between the bonding pads 240 and the first short ring 260, and between the bonding pads 240 and the second short ring 270. That is, there is no interactive voltage influence between the scan lines 220 and the data lines 230 to affect the normal operations of the pixel units 210.
In the conventional method, the first and second short ring 260, 270 are electrically cut off, following by the subsequent processes. During the successive assembly process however, the TFT array substrate 200 likely accumulates electrostatic charges, and at the point, the TFT array substrate 200 has disabled the ESD protection function already, which puts the TFT array substrate 100 in jeopardy to be damaged by an ESD event.